Lithography and patterning are crucial steps in semiconductor fabrication. They involve transferring intricate patterns onto wafer surfaces using light-sensitive materials and specialized equipment. These processes are essential for creating the tiny, complex structures that make up modern electronic devices.

As semiconductor devices shrink, lithography faces new challenges. Advanced techniques like extreme ultraviolet lithography and multiple patterning are being developed to overcome resolution limits. These innovations are key to continuing Moore's Law and enabling smaller, faster, and more efficient chips.

Lithography process overview

• Lithography is a crucial step in semiconductor device fabrication that transfers patterns from a mask onto a thin layer of photoresist on the wafer surface
• The lithography process involves several steps, including photoresist coating, exposure, post-exposure baking, development, and hard baking
• Understanding the lithography process is essential for creating high-resolution patterns and maintaining critical dimensions in semiconductor devices

Photoresist coating

• Photoresist is a light-sensitive polymer that is spin-coated onto the wafer surface to form a thin, uniform layer
• The thickness of the photoresist layer depends on the desired resolution and the exposure system used
• Adhesion promoters, such as hexamethyldisilazane (HMDS), are often applied before photoresist coating to improve adhesion between the photoresist and the wafer surface

Exposure systems

• Exposure systems use light or other radiation sources to transfer the pattern from the mask onto the photoresist layer
• Common exposure systems include contact, proximity, and projection printing
  • Contact printing involves direct contact between the mask and the photoresist, resulting in high resolution but potential mask damage
  • Proximity printing maintains a small gap between the mask and the photoresist, reducing mask damage but sacrificing resolution
  • Projection printing uses a lens system to project the mask pattern onto the photoresist, enabling high resolution and reduced mask wear

Post-exposure baking

• After exposure, the wafer undergoes a post-exposure bake (PEB) to activate the chemical reactions in the exposed regions of the photoresist
• The PEB step helps to reduce standing waves and improve the resist profile by promoting acid diffusion in chemically amplified resists
• Precise temperature control during PEB is crucial for maintaining critical dimensions and minimizing pattern distortion

Development

• During development, the exposed (or unexposed) regions of the photoresist are selectively dissolved using a developer solution
• The choice of developer depends on the type of photoresist used (positive or negative) and the desired resist profile
• Development time and temperature must be carefully controlled to achieve the desired pattern dimensions and avoid pattern collapse or lifting

Hard baking

• After development, the wafer undergoes a hard bake step to further crosslink the remaining photoresist and improve its thermal and chemical stability
• Hard baking helps to prevent pattern deformation during subsequent etching or ion implantation steps
• The hard bake temperature and duration must be optimized to maintain the resist profile and minimize thermal stress

Photolithography vs next-gen lithography

Optical lithography limitations

• Conventional optical lithography faces challenges in patterning sub-10nm features due to the diffraction limit of light
• The minimum feature size that can be resolved using optical lithography is given by the Rayleigh criterion: $CD = k_1 \frac{\lambda}{NA}$, where $CD$ is the critical dimension, $k_1$ is a process-dependent factor, $\lambda$ is the exposure wavelength, and $NA$ is the numerical aperture of the lens system
• To overcome these limitations, various resolution enhancement techniques and next-generation lithography methods have been developed

Extreme ultraviolet (EUV) lithography

• EUV lithography uses a shorter wavelength (13.5 nm) to enable patterning of sub-10nm features
• EUV systems require specialized optics, such as multilayer reflective mirrors and pellicle-free masks, due to the strong absorption of EUV radiation by most materials
• Challenges in EUV lithography include source power, mask defects, and resist performance

Electron beam lithography

• Electron beam lithography (EBL) uses a focused electron beam to directly write patterns onto the resist without the need for a mask
• EBL offers high resolution (sub-10nm) and flexibility in pattern design but suffers from low throughput due to the serial nature of the writing process
• Applications of EBL include mask writing, nanostructure fabrication, and direct-write patterning for low-volume production

Nanoimprint lithography

• Nanoimprint lithography (NIL) is a mechanical patterning method that uses a mold to transfer patterns onto the resist
• NIL can achieve high resolution (sub-10nm) and high throughput by parallel patterning using a single mold
• Challenges in NIL include mold fabrication, defect control, and overlay accuracy

Photoresists for lithography

Positive vs negative photoresists

• Photoresists are classified as positive or negative based on their solubility change upon exposure
• In positive photoresists, the exposed regions become more soluble in the developer, resulting in the removal of exposed areas after development
• In negative photoresists, the exposed regions become less soluble in the developer, resulting in the removal of unexposed areas after development

Photoresist composition

• Photoresists are composed of a polymer resin, a photoactive compound (PAC), and a solvent
• The polymer resin determines the mechanical and thermal properties of the photoresist
• The PAC is responsible for the solubility change upon exposure, either through photochemical reactions (in conventional resists) or acid generation (in chemically amplified resists)
• The solvent controls the viscosity and coating properties of the photoresist

Photoresist properties and selection

• Key properties of photoresists include resolution, sensitivity, contrast, and etch resistance
• Resolution refers to the smallest feature size that can be reliably patterned using a given photoresist and exposure system
• Sensitivity determines the exposure dose required to achieve the desired solubility change in the photoresist
• Contrast is a measure of the photoresist's ability to distinguish between exposed and unexposed regions
• Etch resistance is crucial for maintaining pattern fidelity during subsequent etching steps
• Photoresist selection depends on the specific application, exposure system, and process requirements

Resolution enhancement techniques

Optical proximity correction (OPC)

• OPC is a computational technique that modifies the mask pattern to compensate for optical proximity effects and improve pattern fidelity
• OPC algorithms add sub-resolution assist features (SRAFs) and adjust the geometry of the main features to achieve the desired pattern on the wafer
• Rule-based OPC applies predetermined corrections based on pattern geometry, while model-based OPC uses lithography simulation to optimize the corrections

Phase-shift masks (PSM)

• PSM exploit the phase of light to improve resolution and contrast
• Alternating PSM use phase shifters to introduce a 180° phase difference between adjacent features, creating destructive interference and improving contrast
• Attenuated PSM use partially transmitting phase shifters to reduce the intensity of the background light and improve resolution

Off-axis illumination (OAI)

• OAI techniques modify the illumination source to improve resolution and depth of focus
• Annular illumination uses a ring-shaped source to enhance the resolution of dense patterns
• Dipole illumination uses two poles in the source to improve the resolution of periodic patterns along a specific direction
• Quadrupole illumination uses four poles to enhance the resolution of periodic patterns along two perpendicular directions

Multiple patterning

• Multiple patterning techniques involve splitting a dense pattern into multiple less-dense patterns, which are patterned sequentially using separate lithography and etching steps
• Double patterning (DP) and quadruple patterning (QP) are commonly used to achieve sub-20nm resolution using conventional 193nm immersion lithography
• Challenges in multiple patterning include overlay control, pattern decomposition, and process complexity

Lithography process control

Critical dimension (CD) control

• CD control refers to the ability to maintain the desired feature sizes within a specified tolerance across the wafer and from wafer to wafer
• Factors affecting CD control include exposure dose, focus, resist thickness, and etch bias
• CD uniformity is monitored using in-line metrology techniques, such as scatterometry and critical dimension scanning electron microscopy (CD-SEM)

Overlay accuracy

• Overlay accuracy measures the alignment between successive lithography steps, ensuring that the patterns from different layers are properly aligned
• Factors influencing overlay accuracy include wafer distortion, lens distortion, and alignment mark quality
• Overlay is measured using specialized targets and optical or electron beam metrology tools

Defect inspection and metrology

• Defect inspection is crucial for identifying and classifying defects that may impact device performance or yield
• Optical and electron beam inspection tools are used to detect defects on the wafer surface, such as particles, pattern defects, and residues
• Metrology techniques, such as critical dimension (CD) measurements and thin film thickness measurements, provide quantitative data on the lithography process performance
• Feedback from defect inspection and metrology is used to optimize the lithography process and improve yield

Advanced patterning techniques

Directed self-assembly (DSA)

• DSA is a bottom-up patterning approach that uses block copolymers to create ordered nanostructures
• Block copolymers consist of two or more chemically distinct polymer chains that can self-assemble into periodic nanodomains
• DSA can be used to enhance the resolution of conventional lithography by aligning the block copolymer domains to pre-patterned guide features
• Challenges in DSA include defect control, pattern placement accuracy, and integration with existing lithography processes

Spacer-defined multiple patterning

• Spacer-defined multiple patterning is a technique that uses sacrificial spacers to double the pattern density
• The process involves patterning a set of mandrels, depositing a conformal spacer layer, and selectively removing the mandrels to leave behind a dense array of spacers
• Multiple iterations of spacer patterning can be used to further increase the pattern density
• Advantages of spacer-defined multiple patterning include high resolution, self-alignment, and reduced overlay requirements

Block copolymer lithography

• Block copolymer lithography exploits the self-assembly of block copolymers to create periodic nanostructures
• The process involves depositing a block copolymer film on a substrate, inducing phase separation through annealing, and selectively removing one of the polymer domains
• Block copolymer lithography can be used as a stand-alone patterning technique or in combination with conventional lithography for pattern multiplication
• Challenges in block copolymer lithography include defect density, pattern orientation control, and integration with existing manufacturing processes

Lithography simulation and modeling

Aerial image simulation

• Aerial image simulation predicts the light intensity distribution at the wafer plane based on the mask pattern, illumination source, and lens system
• Simulation tools use scalar or vector diffraction theory to calculate the aerial image, taking into account the effects of partial coherence, aberrations, and polarization
• Aerial image simulation is used to optimize the mask design, illumination source, and process parameters for improved pattern fidelity

Resist profile modeling

• Resist profile modeling simulates the photoresist's response to the aerial image, predicting the 3D shape of the resist pattern after exposure and development
• Resist models take into account the chemical and physical properties of the photoresist, such as absorption, diffusion, and development rates
• Accurate resist modeling is crucial for predicting the effects of exposure dose, focus, and post-exposure bake on the final resist profile

Lithography process optimization

• Lithography process optimization involves finding the best combination of process parameters to achieve the desired pattern quality and yield
• Optimization techniques, such as design of experiments (DOE) and response surface methodology (RSM), are used to systematically explore the process parameter space
• Lithography simulation is used to guide the optimization process by predicting the impact of process changes on the final pattern
• Objectives of lithography process optimization include maximizing the process window, minimizing CD variation, and improving overlay accuracy

Challenges in sub-10nm patterning

EUV source and optics

• EUV lithography requires a high-power, stable, and debris-free EUV source operating at 13.5 nm wavelength
• Current EUV sources based on laser-produced plasma (LPP) or discharge-produced plasma (DPP) face challenges in achieving the required power and stability for high-volume manufacturing
• EUV optics, including multilayer mirrors and pellicle-free masks, must maintain high reflectivity and low defect density to ensure efficient light transmission and pattern fidelity

Resist materials for EUV

• EUV resists must meet stringent requirements for resolution, sensitivity, and line edge roughness (LER)
• Conventional chemically amplified resists (CARs) face challenges in achieving the required resolution and LER at EUV wavelengths due to the increased photon shot noise and the trade-off between resolution, sensitivity, and LER
• Novel resist materials, such as metal-oxide resists and molecular resists, are being developed to address the limitations of CARs for EUV lithography

Stochastic effects and line edge roughness

• Stochastic effects, such as photon shot noise and molecular fluctuations, become increasingly prominent at sub-10nm feature sizes
• These effects lead to increased line edge roughness (LER) and line width roughness (LWR), which can impact device performance and yield
• Strategies to mitigate stochastic effects include the use of high-sensitivity resists, optimized exposure and development conditions, and post-lithography smoothing techniques, such as resist reflow and hydrogen annealing